The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
Many of these semiconductor devices are now affected by conditions brought about by their small size and density on the substrate. With respect to poly-emitter devices and gate oxide transistors, the thickness of the oxide layer is crucial to the speed and performance of the device. Therefore, measuring the thickness of the oxide or dielectric layers on a regular basis is important in monitoring the performance of the wafer processing line. In addition, due to wafer processing anomalies an interfacial oxide layer is sometimes formed through oxidation between the silicon substrate and a polycrystalline layer being deposited on the substrate. This increases the effective thickness of the dielectric layer of the transistor, which affects the device's speed and performance. Even though TEM (transmission electron microscopy) is currently the tool of choice to image cross sections of the thin oxide layers, lengthy sample preparation time required by TEM as well increasingly lower levels of resolution achieved by TEM (as oxide layer thickness decrease by virtue of current wafer processing techniques) is quickly forcing chip designers to look for other alternatives in measuring dielectric layers in integrated circuit devices.